The present invention relates generally to a semiconductor package, and more particularly to a semiconductor package having an interposer.
In general, a semiconductor package includes a substrate and a semiconductor chip mounted on the substrate. In order to electrically connect the semiconductor chip with the substrate, a wire bonding method or a bump forming method is being used.
In the case of the wire bonding method, a semiconductor chip is attached to a substrate by the medium of an adhesive, and the bonding pads of the semiconductor chip and the bond fingers of the substrate are connected with each other by metal wires through a wire bonding process such that the substrate and the semiconductor chip are electrically connected with each other. However, in this case, since exchange of electrical signals between the semiconductor chip and the substrate is implemented through the metal wires, the operating speed of the semiconductor package may become slow, and since a number of wires are used, the electrical characteristics of the semiconductor chip may deteriorate.
In the case of the bump forming method, a semiconductor chip is flip-chip bonded to a substrate by the medium of metal bumps such that the substrate and the semiconductor chip are electrically connected with each other by the bumps. Then, an underfill process for filling the space between the semiconductor chip and the substrate is performed.
With increasing demand for large-capacity, miniaturized and reliable semiconductor product, various packaging technologies for semiconductor devices are being developed. For example, packaging technologies to achieve chip size packaging and to increase mechanical and electrical reliability after mounting are being developed.
As one of these technologies, a technology increasing a number of electrode pads arranged in a limited space has been suggested so as to achieve a fine pitch during flip-chip bonding process. However, in this case, the bumps may be short-circuited, e.g., with adjacent bumps, and the electrical connection between the substrate and the semiconductor chip may become unstable.
Further, in order to prevent the bumps from being short-circuited and decrease the entire height of a package, a method for decreasing the height between the substrate and the semiconductor chip has been proposed. Nevertheless, in the case, when performing an underfill process to fill the space between the substrate and the semiconductor chip, voids may be created.
Therefore, a method for stabilizing the electrical connection between a substrate and a semiconductor chip and improving the reliability of a package is demanded.